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Integrated Circuit Systems, Inc.
ICS954101
Programmable Timing Control HubTM for Desktop P4TM Systems
Recommended Application: CK410 clock, Intel Yellow Cover part Output Features: * 2 - 0.7V current-mode differential CPU pairs * 6 - 0.7V current-mode differential SRC pair for SATA and PCI-E * 1 - 0.7V current-mode differential CPU/SRC selectable pair * 6 - PCI (33MHz) * 3 - PCICLK_F, (33MHz) free-running * 1 - USB, 48MHz * 1 - DOT, 96MHz, 0.7V current differential pair * 1 - REF, 14.318MHz Key Specifications: * CPU outputs cycle-cycle jitter < 85ps * SRC output cycle-cycle jitter <125ps * PCI outputs cycle-cycle jitter < 500ps * +/- 300ppm frequency accuracy on CPU & SRC clocks Functionality
FS_C1 0 0 0 0 1 1 1 1 FS_B2 FS_A2 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPU SRC MHz MHz 266.66 100.00 133.33 100.00 200.00 100.00 166.66 100.00 333.33 100.00 100.00 100.00 400.00 100.00 RESERVED PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 REF MHz 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 USB MHz 48.00 48.00 48.00 48.00 48.00 48.00 48.00 48.00 DOT MHz 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00
Features/Benefits: * Supports tight ppm accuracy clocks for Serial-ATA and PCI-Express * Supports spread spectrum modulation, 0 to -0.5% down spread * * * Supports CPU clks up to 400MHz Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Supports undriven differential CPU, SRC pair in PD# for power management.
Pin Configuration
VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 PCICLK_F1 PCICLK_F2 VDD48 USB_48MHz GND DOTT_96MHz DOTC_96MHz FS_B/TEST_MODE Vtt_PwrGd#/PD FS_A_410 SRCCLKT1 SRCCLKC1 VDDSRC SRCCLKT2 SRCCLKC2 SRCCLKT3 SRCCLKC3 SRCCLKT4_SATA SRCCLKC4_SATA VDDSRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCICLK2 PCICLK1 PCICLK0 FS_C/TEST_SEL REFOUT GND X1 X2 VDDREF SDATA SCLK GND CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 IREF GNDA VDDA CPUCLKT2_ITP/SRCCLKT_7 CPUCLKC2_ITP/SRCCLKC_7 VDDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 GND
1. FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.
56-pin SSOP & TSSOP
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ICS954101
Integrated Circuit Systems, Inc.
ICS954101
Pin Description
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NAME VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 PCICLK_F1 PCICLK_F2 VDD48 USB_48MHz GND DOTT_96MHz DOTC_96MHz FS_B/TEST_MODE PIN TYPE PWR PWR OUT OUT OUT PWR PWR I/O OUT OUT PWR OUT PWR OUT OUT IN DESCRIPTION Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP#. ITP_EN: latched input to select pin functionality 1 = CPU_ITP pair 0 = SRC pair Free running PCI clock not affected by PCI_STOP# . Free running PCI clock not affected by PCI_STOP# . Power pin for the 48MHz output.3.3V 48.00MHz USB clock Ground pin. True clock of differential pair for 96.00MHz DOT clock. Complement clock of differential pair for 96.00MHz DOT clock. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 3.3V tolerant low threshold input for CPU frequency selection. This pin requires CK410 FSA. Refer to input electrical characteristics for Vil_FS and Vih_FS threshold values. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC/SATA pair. Complement clock of differential SRC/SATA pair. Supply for SRC clocks, 3.3V nominal
17
Vtt_PwrGd#/PD
IN
18 19 20 21 22 23 24 25 26 27 28
FS_A_410 SRCCLKT1 SRCCLKC1 VDDSRC SRCCLKT2 SRCCLKC2 SRCCLKT3 SRCCLKC3 SRCCLKT4_SATA SRCCLKC4_SATA VDDSRC
IN OUT OUT PWR OUT OUT OUT OUT OUT OUT PWR
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ICS954101
Pin Description (Continued)
Pin # 29 30 31 32 33 34 35 PIN NAME GND SRCCLKC5 SRCCLKT5 SRCCLKC6 SRCCLKT6 VDDSRC CPUCLKC2_ITP/SRCCLKC_7 TYPE PWR OUT OUT OUT OUT PWR OUT DESCRIPTION Ground pin. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Complimentary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. 3.3V power for the PLL core. Ground pin for the PLL core. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Ref, XTAL power supply, nominal 3.3V Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ground pin. Reference Clock output 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values. TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table PCI clock output. PCI clock output. PCI clock output.
36 37 38 39
CPUCLKT2_ITP/SRCCLKT_7 VDDA GNDA IREF
OUT PWR PWR OUT
40 41 42 43 44 45 46 47 48 49 50 51 52
CPUCLKC1 CPUCLKT1 VDDCPU CPUCLKC0 CPUCLKT0 GND SCLK SDATA VDDREF X2 X1 GND REFOUT
OUT OUT PWR OUT OUT PWR IN I/O PWR OUT IN PWR OUT
53
FS_C/TEST_SEL
IN
54 55 56
PCICLK0 PCICLK1 PCICLK2
OUT OUT OUT
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Integrated Circuit Systems, Inc.
ICS954101
General Description
ICS954101 follows Intel CK410 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS954101 is driven with a 14.318MHz crystal. It generates CPU outputs up to 400MHz. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support.
Block Diagram
48MHz, USB PLL2 Frequency Dividers 96MHz_DOTT_0 96MHz_DOTC_0 X1 X2 XTAL REFOUT CPUCLKT (2:0) CPUCLKC (2:0) SCLK SDATA Vtt_PWRGD#/PD FS_A FS_B FS_C ITP_EN TEST_MODE TEST_SEL Programmable Spread PLL1 Control Logic Programmable Frequency Dividers STOP Logic SRCCLKT (7:1) SRCCLKC (7:1) PCICLK (5:0) PCICLKF (2:0)
I REF
Power Groups
Pin Number VDD GND 48 51 1,7 2,6 21,28,34 29 37 38 11 13 42 45 Description Xtal, Ref PCICLK outputs SRCCLK outputs Master clock, CPU Analog DOT, USB, PLL_48 CPUCLK clocks
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Integrated Circuit Systems, Inc.
ICS954101
General I2C serial interface information for the ICS954101 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
ACK
Byte N + X - 1 N P Not acknowledge stoP bit
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Integrated Circuit Systems, Inc.
ICS954101
Absolute Max
Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V C C C V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL I IH IIL1 Input Low Current IIL2 Low Threshold Input High Voltage Low Threshold Input Low Voltage Operating Supply Current Powerdown Current Input Frequency 3 Pin Inductance1 Input Capacitance1 Clk Stabilization1,2 Modulation Frequency Tdrive_PD# Tfall_Pd# Trise_Pd# SMBus Voltage V DD Low-level Output Voltage VOLSMBUS Current sinking at VOL = 0.4 V IPULLUP SCLK/SDATA TRI2C Clock/Data Rise Time SCLK/SDATA TFI2C Clock/Data Fall Time
1 2 3
CONDITIONS 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5%, Full Load all diff pairs driven all differential pairs tri-stated VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation CPU output enable after PD# de-assertion PD# fall time of PD# rise time of @ IPULLUP
MIN 2 VSS - 0.3 -5 -5 -200 0.7 VSS - 0.3
TYP
MAX VDD + 0.3 0.8 5
UNITS NOTES V V uA uA uA
VIH_FS VIL_FS IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX TSTAB
VDD + 0.3 0.35 350 500 70 12 14.31818 7 5 6 5 1.8
V V mA mA mA MHz nH pF pF pF ms kHz us ns ns V V mA ns ns
3 1 1 1 1 1,2 1 1 1 2 1 1 1 1 1
30
33 300 5 5 5.5 0.4
2.7 4 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15)
1000 300
Guaranteed by design and characterization, not 100% tested in production. See timing diagrams for timing requirements. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm accuracy on PLL outputs.
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Integrated Circuit Systems, Inc.
ICS954101
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175 MIN 3000 660 -150 -300 250 850 mV 150 1150 550 140 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps 1 1 1 1 1 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 1 TYP MAX UNITS NOTES 1 1
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew Skew Jitter, Cycle to cycle
tr tf d-tr d-tf dt3 tsk3 tsk4 tjcyc-cyc
700 700 125 125 55 100 150
Measurement from differential wavefrom CPU (1:0) VT = 50% CPU (1:0) to CPU_ITP, VT = 50%
45
Measurement from differential 85 ps wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
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Integrated Circuit Systems, Inc.
ICS954101
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage SYMBOL Zo VHigh VLow Vovs Vuds CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope Measurement on single ended signal using absolute value. MIN 3000 660 -150 -300 250 Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V 350 12 -300 9.9970 9.9970 9.8720 175 175 30 30 550 140 300 10.0030 10.0533 700 700 125 125 850 150 1150 TYP MAX UNITS NOTES mV mV mV mV ppm ns ns ns ps ps ps ps 1 1 1 1 1 1 1 1,2 2 2 1,2 1 1 1 1
Crossing Voltage (abs) Vcross(abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle d-Vcross ppm Tperiod Tabsmin tr tf d-tr d-tf dt3
Measurement from differential 45 55 % 1 wavefrom tsk3 SRC(7:0), VT = 50% Skew 250 ps 1 Measurement from differential tjcyc-cyc Jitter, Cycle to cycle 125 ps 1 wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
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Integrated Circuit Systems, Inc.
ICS954101
Electrical Characteristics - PCICLK/PCICLK_F
T A = 0 - 70C; V DD = 3.3 V +/-5% ; C L = 30 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Absolute Min/Max Clock period Clk High Time Clock Low Time Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL ppm T period T abs t h1 t l1 V OH V OL I OH I OL
CONDITIONS see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread 33.33MHz output nominal 33.33MHz output spread
MIN -300 29.99100 29.99100 29.49100 29.49100 12 12 2.4 -33
TYP
MAX 300 30.00900 30.15980 30.50900 30.65980 N/A N/A 0.55 -33
UNITS ppm ns ns ns ns ns ns V V mA mA mA mA V/ns V/ns ns ns % ps ps
Notes 1,2 2 2 2 2 1 1
I OH = -1 mA I OL = 1 mA V OH @MIN = 1.0 V V OH@ MAX = 3.135 V V OL @ MIN = 1.95 V V OL @ MAX = 0.4 V Rising edge rate Falling edge rate V OL = 0.4 V, V OH = 2.4 V V OH = 2.4 V, V OL = 0.4 V V T = 1.5 V V T = 1.5 V V T = 1.5 V
30 38 1 1 0.5 0.5 45 4 4 2 2 55 500 500
t r1 t f1 dt1 tsk1 t jc y c -c y c
1 1 1 1 1 1 1
Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
Electrical Characteristics - U SB_48MH z
T A = 0 - 70C; V DD = 3.3 V +/-5% ; CL = 20 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Absolute Min/Max Clock period Clk High Time Clock Low Time Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Jitter, Cycle to cycle
1 2
SYMBOL ppm T period T abs t h1 t l1 I OH I OL
CONDITIONS see Tperiod min-max values 48.0000MHz output nominal Nominal
MIN -100 20.82570 20.48125 8.094 7.694 -33 30 1 1 1 1 45
TYP
MAX 100 20.83400 21.18542 10.036 9.836 -33 38 2 2
UNITS Notes ppm ns ns ns ns mA mA mA mA V/ns V/ns ns ns % ps 1,2 2 2 1 1
V OH @ MIN = 1.0 V V OH@ MAX = 3.135 V V OL @MIN = 1.95 V V OL @ MAX = 0.4 V Rising edge rate Falling edge rate V OL = 0.4 V, V OH = 2.4 V V OH = 2.4 V, V OL = 0.4 V V T = 1.5 V V T = 1.5 V
1 1 1 1 1 1
t r1 t f1 dt1 t jc y c -c y c
1.4 1.3 48
2 2 55 350
Guaranteed by design, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
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Integrated Circuit Systems, Inc.
ICS954101
Electrical Characteristics - DOT, 96MHz 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle SYMBOL Zo VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm Tperiod Tabsmin tr tf d-tr d-tf dt3 CONDITIONS VO = Vx Statistical measurement on single ended signal Measurement on single ended signal using MIN 3000 660 -150 -300 250 Variation of crossing over all edges see Tperiod min-max -100 values 96.00MHz nominal 10.4135 96.00MHz nominal VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V 10.1635 175 175 700 700 125 125 550 140 100 10.4198 850 150 1150 TYP MAX UNITS mV mV mV mV ppm ns ns ps ps ps ps NOTES 1 1 1 1 1 1 1 1,2 2 1,2 1 1 1 1
Measurement from 45 55 % 1 differential wavefrom Measurement from tjcyc-cyc Jitter, Cycle to cycle 250 ps 1 differential wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFoutput is at 14.31818MHz
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Integrated Circuit Systems, Inc.
ICS954101
Electrical Characteristics - REF-14.318MHz
T A = 0 - 70C; V DD = 3.3 V +/-5% ; CL = 20 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Absolute Min/Max Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew Duty Cycle Jitter
1
SYMBOL ppm T period T abs V OH V OL I OH I OL t r1 t f1 ts k 1 d t1 t jc y c -c y c
CONDITIONS see Tperiod min-max values 14.318MHz output nominal Nominal I OH = -1 mA I OL = 1 mA V OH @MIN = 1.0 V, V OH@MAX = 3.135 V V OL @MIN = 1.95 V, V OL @MAX = 0.4 V V OL = 0.4 V, V OH = 2.4 V V OH = 2.4 V, V OL = 0.4 V V T = 1.5 V V T = 1.5 V V T = 1.5 V
MIN -300 69.82700 68.82033 2.4
TYP
MAX 300 69.85500 70.86224
UNITS ppm ns ns V V mA mA ns ns ps % ps
NOTES 1 1 2 1 1 1 1 1 1 1 1 1
0.4 -29 29 1 1 45 -23 27 2 2 500 55 1000
Guaranteed by design, not 100% tested in production.
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Integrated Circuit Systems, Inc.
ICS954101
I2C Table: Read-Back Register Byte 0 Pin # 35,36 Bit 7 32,33 Bit 6 30,31 Bit 5 26,27 Bit 4 24,25 Bit 3 22,23 Bit 2 19,20 Bit 1 Bit 0
Name CPUCLK2/RCCLK7 Enable SRCCLK6 Enable SRCCLK5 Enable SRCCLK4 Enable SRCCLK3 Enable SRCCLK2 Enable SRCCLK1 Enable
Control Function Type Output Enable RW RW Output Enable Output Enable RW Output Enable RW Output Enable RW Output Enable RW Output Enable RW RESERVED
0 DISABLE DISABLE DISABLE DISABLE DISABLE DISABLE DISABLE
1 ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE ENABLE
PWD 1 1 1 1 1 1 1
I2C Table: Spreading and Device Behavior Control Register Byte 1 Pin # Name 54 PCI_F0 Enable Bit 7 14,15 Bit 6 DOT_96MHz 12 Bit 5 USB_48MHz Enable 52 Bit 4 REFOUT Enable Bit 3 40,41 Bit 2 CPUT1/CPUC1 43,44 Bit 1 CPUT0/CPUC0 Bit 0 Spread Spectrum Mode
Control Function Output Enable Output Enable Output Enable Output Enable RESERVED Output Enable Output Enable Spread Off
Type RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable SPREAD OFF
1 Enable Enable Enable Enable Enable Enable SPREAD ON
PWD 1 1 1 1 1 1 1 0
I2C Table: Output Control Register Byte 2 Pin # 5 Bit 7 4 Bit 6 3 Bit 5 56 Bit 4 55 Bit 3 54 Bit 2 10 Bit 1 9 Bit 0
Name PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 PCI_F2 Enable PCI_F1 Enable
Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
I2C Table: Output Control Register Byte 3 Pin # Name 35,35 Bit 7 CPU_ITP/SRCCLK7 32,33 Bit 6 SRCCLK6 30,31 Bit 5 SRCCLK5 26,27 Bit 4 SRCCLK4 24,25 Bit 3 SRCCLK3 22,23 Bit 2 SRCCLK2 19,20 Bit 1 SRCCLK1 Bit 0
Control Function Free-Running Control default: not affected by PCI/SRC_STOP (Byte 6, bit 3) RESERVED
Type RW RW RW RW RW RW RW
0 Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running
1 Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable
PWD 0 0 0 0 0 0 0 0
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ICS954101
I2C Table: Output Control Register Byte 4 Pin # Bit 7 14,15 Bit 6 10 Bit 5 9 Bit 4 8 Bit 3 Bit 2 Bit 1 Bit 0
Name DOT_96MHz PCI_F2 PCI_F1 PCI_F0
Control Function RESERVED Driven in PD Free-Running Control not affected by RESERVED RESERVED RESERVED
Type RW RW RW RW
0 Driven Free-Running Free-Running Free-Running
1 Hi-Z Stoppable Stoppable Stoppable
PWD 1 1 1 1 1 1 1 1
I2C Table: Output Control Register Byte 5 Pin # Name 19,20,22,23, 24,25,26,27,30,31, Bit 7 SRC Stop Drive Mode 32,33,35,36 Bit 6 Bit 5 Bit 4 19,20,22,23, 24,25,26,27,30,31, Bit 3 SRC PD Drive Mode 32,33,35,36 35,36 CPUCLK_ITP Bit 2 40,41 CPUCLK1 Bit 1 43,44 Bit 0 CPUCLK0
Control Function Drive Mode in PCI_Stop RESERVED RESERVED RESERVED Drive Mode in PD Drive Mode in PD Drive mode in PD Drive mode in PD
Type RW
0 Driven
1 Hi-Z
PWD 0 0 0 0
RW RW RW RW
Driven Driven Driven Driven
Hi-Z Hi-Z Hi-Z Hi-Z
0 0 0 0
I2C Table: Output Control Register Byte 6 Pin # Bit 7 Bit 6 Bit 5 Bit 4 52 17,18,19,20,22,23, 24,25,26,27,30,31, 32,33,35,36 54,55,56,3,4,5,8,9, 10 -
Name Test Mode Selection Test Clock Mode Entry REFOUT Strength
Control Function Test Mode Selection Test Mode RESERVED Strength Prog Stop all PCI and SRC clocks readback readback readback
Type RW RW RW
0 Hi-Z Disable 1X
1 REF/N Enable 2X
PWD 0 0 0 1
Bit 3
PCI/SRC_STOP
RW
Disabled, all Enabled, all stoppable PCI stoppable PCI and SRC clocks and SRC clocks are running are stopped. -
1
Bit 2 Bit 1 Bit 0
FS_C FS_B FS_A
R R R
LATCHED LATCHED LATCHED
I2C Table: Vendor & Revision ID Register Byte 7 Pin # Name Bit 7 RID3 Bit 6 RID2 Bit 5 RID1 Bit 4 RID0 Bit 3 VID3 Bit 2 VID2 Bit 1 VID1 Bit 0 VID0
Control Function REVISION ID
VENDOR ID
Type R R R R R R R R
0 -
1 -
PWD 0 0 0 0 0 0 0 1
0815E--06/01/05
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Integrated Circuit Systems, Inc.
ICS954101
Test Clarification Table
Comments HW TEST FS_C/TEST_ FS_B/TEST_ ENTRY BIT SEL MODE B6b6 HW PIN HW PIN 0 X 0 1 0 X 1 0 X 1 1 X SW REF/N or HI-Z B6b7 OUTPUT X NORMAL 0 HI-Z 1 REF/N 0 REF/N
* FS_C/TEST_SEL is a 3-level latched input. o Power-up w/ V >= 2.0V to select TEST o Power-up w/ V < 2.0V to have pin function as FS_C. * When pin is FS_C, VIH_FS and VIL_FS levels apply. * FS_B/TEST_MODE is a low-threshold input o VIH_FS and VIL_FS levels apply. o TEST_MODE is a real time input * TEST_SEL can be invoked after power up through SMBus B6b6. o If TEST is selected by B6b6, only B6b7 controls TEST_MODE. The FS_B/TEST_Mode pin is not used. * Power must be cycled to exit TEST.
1
1
X
1
REF/N
0
X
1
0
HI-Z
0
X
1
1
REF/N
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B6b7: 1= REF/N, Default = 0 (HI-Z)
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Integrated Circuit Systems, Inc.
ICS954101
N
c
56-Lead, 300 mil Body, 25 mil, SSOP SYMBOL A A1 b c D E E1 e h L N a VARIATIONS In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
L
INDEX AREA
E1
E
12 D h x 45
A A1
-Ce
b SEATING PLANE .10 (.004) C
N 56
D mm. MIN 18.31 MAX 18.55 MIN .720
D (inch) MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS954101yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device
0815E--06/01/05
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Integrated Circuit Systems, Inc.
ICS954101
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 56
10-0039
-Ce
b SEATING PLANE
aaa C
D mm. MIN MAX 13.90 14.10
D (inch) MIN .547 MAX .555
Reference Doc.: JEDEC Publicat ion 95, M O-153
Ordering Information
ICS954101yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device
0815E--06/01/05
16
Integrated Circuit Systems, Inc.
ICS954101
Revision History
Rev. E Issue Date Description 1. Updated Block Diagram. 6/1/2005 2. Update LF Ordering Information to RoHS Compliant. Page # 4,15-16
0815E--06/01/05
17

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